Improvements in hole mobility have been realized in PMOS devices (i.e., metal-oxide-semiconductor (MOS) devices with n-type, or n-doped, active-device regions and p-type transistor channels), or transistors, by compressively stressing the channels of such devices. Similar improvements in electron mobility have been realized in NMOS devices (i.e., MOS devices with p-type, or p-doped, active-device regions and n-type transistor channels), or transistors, when the channels thereof experience tensile strain.
A number of techniques have been researched to compressively stress PMOS regions, including the inclusion of a strained layer of silicon-germanium (SiGe) within a silicon active-device (e.g., source or drain) region to compressively stress the active-device region, which results in an increase in hole mobility of up to 50%. Strained silicon-germanium layers have also been embedded in the active-device regions of NMOS devices to compressively stress the channels between the active-device regions.
When silicon-germanium is used, a thin layer of silicon-germanium is formed, typically by ultra-high vacuum chemical vapor deposition (CVD) techniques. The layer of silicon-germanium is then capped with a silicon film, which prevents incorporation of germanium into the gate oxide. Lattice mismatches between the silicon-germanium layer and the silicon capping layer generate the desired compressive stress or tensile stress. The silicon-germanium layer may be graded to a relaxed or unstrained state, which generates stress in the silicon capping layer. If both the silicon-germanium layer and the silicon capping layer are thin, they will both be strained. At high gate voltages, the germanium-silicon-silicon capping layer structure has dual-channel characteristics. While many of the carriers or holes are located in the silicon germanium layer, some carriers or holes are also present at the interface between the silicon capping layer and the gate oxide. Unfortunately, the ultra-high vacuum CVD techniques that have been used to fabricate silicon-germanium layers are extremely expensive and, thus, not conducive to use in large-scale semiconductor device fabrication processes.
A number of other experimental techniques for stressing active-device regions of semiconductor device structures have also been developed. Tensile strain has been generated in the channels of NMOS devices by using silicon carbide (SiC) in the active-device regions. Semiconductor device structures have also been bent (which may, e.g., be effected in packaging and encapsulation) to stress the transistor channels. In addition, semiconductor device structures have been fabricated with stress-inducing silicon nitride capping layers.
It would be desirable to develop a process by which transistor channels of semiconductor device structures may be stressed economically and on a scale that is suitable for incorporation into semiconductor device fabrication.